1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of driving the same, and more specifically, relates to a semiconductor memory device that performs writing of information stored as resistance states of variable resistance elements of memory cells by application of a voltage pulse and a method of driving the same.
2. Description of the Related Art
In recent years, a new type of non-volatile semiconductor memory device to take place of a flash memory is being widely developed. Among those, a RRAM using a phenomenon of an occurrence of a change in a resistance due to application of a voltage to a variable resistance film such as a transition metal oxide or the like is commonly subjected to research and development since it is advantageous in regards to a limit in miniaturization compared to the flash memory, and is capable of a high-speed data writing.
As a configuration of a memory cell array using the RRAM, there has been conventionally used, as described in Japanese Unexamined Patent Publication No. 2002-151661, a 1T1R type memory cell array capable of restricting a leak current and a sneak current flowing in unselected memory cells upon performing the writing and reading of information stored in variable resistance elements of selected memory cells by serially connecting transistors for cell selection to variable resistance elements of memory cells.
FIG. 8 shows a cell array configuration of the conventionally-used RRAM. In a memory cell array 200, R11 to Rn1, R12 to Rn2, . . . , R1m to Rnm as variable resistance elements and Q11 to Qn1, Q12 to Qn2, . . . , Q1m to Qnm as transistors for cell selection are arranged respectively in a row direction (a lateral direction in the figure) and a column direction (a vertical direction in the figure) in a matrix. In each of the memory cells, one terminal of the variable resistance element and one terminal of the transistor are connected, and the other terminals of the variable resistance elements of the memory cells arranged in the same row are respectively connected to bit lines BL1 to BLm extending in the row direction; the other terminals of the transistors of the memory cells arranged in the same column are connected to a common line CML that is common for all of the memory cells; and word lines WL1 to WLn extending in the column direction are respectively connected to gate terminals of the transistors of the memory cells arranged in the same column.
Write voltages are supplied through Power lines V1 and V2 from outside, and the voltage from the power line V1 is applied to the bit lines BL1 to BLm, and the voltage from the power line V2 is applied to the common line CML respectively via transistors in a write voltage applying circuit 201. Further, the bit lines BL1 to BLm and the common line CML are short-circuited via transistors in an initialization circuit 202, and by applying the voltage to the bit lines from a common line side, a bit line voltage that is in a former writing operation voltage state due to an influence of a parasitic capacity of wirings between the bit line and the variable resistance elements connected to the bit line can be initialized.
FIG. 9 shows a timing chart upon writing a variable resistance element R11 of FIG. 8. Hereinafter, an operation to lower a resistance state of a variable resistance element to a low resistance and increase a current flowing in a memory cell is referred to as “set (program)”, and an operation to increase the resistance state of the variable resistance element to a high resistance and decrease the current flowing in the memory cell is referred to as “reset (erase)”. Definitions of set and reset may of course be opposite of the above. Further, such set and reset in combination is referred to as “write”.
At time t1, the word line WL1 is raised to a voltage VWLS (representative value: 4 V) upon setting or to a voltage VWLR (representative value: 6 V) upon resetting, and then, φ0, φ11, φ22 to φ2m are raised at time t2 to perform an initialization operation. That is, the voltage of the power line V1 is applied to a selected bit line BL1 via a transistor of the write voltage applying circuit 201, the voltage of the power line V2 is applied to the common line CML, and further, a voltage identical to that of the common line CML is applied to unselected bit lines BL2 to BLm via a transistor of the initialization circuit 202, to initialize the voltage of the unselected bit lines. At this time, the voltage of the power lines V1 and V2 is the same initialization voltage VPRE (representative value: 1.5 V), and as a result, the common line CML and all of the bit lines BL1 to BLm are precharged to the same voltage VPRE.
Thereafter, during time t4 to t5, a write voltage pulse is applied to the power lines V1 and V2. That is, upon the setting, the power line V1 is changed to a voltage VSET (representative value: 3 V) and the power line V2 is changed to GND, and current is made to flow toward the common line CML from the selected bit line BL1 via R11, Q11. On the other hand, upon the resetting, the power line V1 is changed to GND and the power line V2 is changed to a voltage VRST (representative value: 3 V), and the current is made to flow toward the selected bit line BL1 from the common line CML via Q11, R11.
In the array configuration shown in FIG. 8, although the resistance values of the variable resistance elements can be changed, a problem occurs in operations with voltage pulses having short time width, that is, a high-speed operation is impossible. A reason therefor will be described below.
In order for the variable resistance elements to cause changes in their resistance, a voltage larger than a certain value must be applied for over a certain period of time. An interval Δt between time t4 and t5 must be set so as to satisfy such a condition.
FIG. 10 schematically shows a voltage change of a voltage pulse applied to one terminal of a variable resistance element in a case where a voltage pulse of Δt=8 ns is applied to the common line. A speed of the voltage change varies depending on magnitudes of a parasitic resistance and a parasitic capacity of wirings to be driven. In FIG. 10, (a) and (b) show the waveforms of the voltage pulses applied to one terminal of the variable resistance element in a case of the parasitic resistance and the parasitic capacity of the common line respectively being 50Ω and 10 pF, and a time constant RC determined by the parasitic resistance and the parasitic capacity being 0.5 ns. In FIG. 10, (c) and (d) show the waveforms of the voltage pulses applied to one terminal of the variable resistance element in a case of the parasitic resistance and the parasitic capacity of the common line respectively being 250Ω and 50 pF, and the time constant RC determined by the parasitic resistance and the parasitic capacity being 12.5 ns. Particularly, at the moment of time t4, since the transistors for precharging connected to the unselected bit lines of φ22 to φ2m are open, the parasitic resistance and the parasitic capacity belonging to the driven wirings are very large (representative value of the parasitic resistance: 300Ω, representative value of the parasitic capacity: 100 pF) since the parasitic resistance and the parasitic capacity of the unselected bit lines are added in addition to the parasitic resistance and the parasitic capacity of the common line itself.
Therefore, the voltage change in the voltage pulse applied to one terminal of the variable resistance element do not exhibit a high-speed change as shown in (a) and (b) of FIG. 10, and rather is extremely slow as shown in (c) and (d) of FIG. 10. In the ease where the time interval Δt is short and insufficient, there may be a case in which the resistance change in the variable resistance element does not occur for not having reached VRST or VSET. In order to avoid such a problem, Δt must be made sufficiently long.